NISC is a new technology for designing custom processors and IPs. NISC eliminates the instruction abstraction and gives the complete control of hardware units to the compiler. The inputs of the NISC compiler are processor datapath netlist and application C code. The output is control signal values of hardware units at every cycle. My research on NISC include:

• Designing a new XML-based Architecture Description Language (ADL) for synthesis, simulation, and compilation of custom NISC processors. Once a new NISC processor is capture in our ADL, the entire NISC toolset is retargeted for that processor. The format is also extended for prototyping of multi-processor systems on FPGA.
• Developing a RTL generator software to produce synthesizable Verilog code for custom processors described in our ADL. The RTL generator also facilitates fast FPGA prototyping by producing FPGA cores for memory, dividers, and other hardcore units.
• Setting up case-studies using NISC: 2-D Discrete Cosine Transform (DCT), JPEG, and MP3. The designs are implemented on a FPGA board.
• Designing double-handshake master/slave bus interface for NISC. In multi-core systems, each core must have proper hardware interface and software driver to communicate with other cores. For NISC, we developed a double-handshake bus interface.

NISC prototypes for DCT are available here .